D0 /2         RCL r/m8,1         Rotate 9 bits (CF, r/m8) left once

D2 /2         RCL r/m8,CL         Rotate 9 bits (CF, r/m8) left CL times

C0 /2 ib         RCL r/m8,imm8         Rotate 9 bits (CF, r/m8) left imm8 times

D1 /2         RCL r/m16,1         Rotate 17 bits (CF, r/m16) left once

D3 /2         RCL r/m16,CL         Rotate 17 bits (CF, r/m16) left CL times

C1 /2 ib         RCL r/m16,imm8         Rotate 17 bits (CF, r/m16) left imm8 times

D1 /2         RCL r/m32,1         Rotate 33 bits (CF, r/m32) left once

D3 /2         RCL r/m32,CL         Rotate 33 bits (CF, r/m32) left CL times

C1 /2 ib         RCL r/m32,imm8         Rotate 33 bits (CF, r/m32) left imm8 times

D0 /3         RCR r/m8,1         Rotate 9 bits (CF, r/m8) right once

D2 /3         RCR r/m8,CL         Rotate 9 bits (CF, r/m8) right CL times

C0 /3 ib         RCR r/m8,imm8         Rotate 9 bits (CF, r/m8) right imm8 times

D1 /3         RCR r/m16,1         Rotate 17 bits (CF, r/m16) right once

D3 /3         RCR r/m16,CL         Rotate 17 bits (CF, r/m16) right CL times

C1 /3 ib         RCR r/m16,imm8         Rotate 17 bits (CF, r/m16) right imm8 times

D1 /3         RCR r/m32,1         Rotate 33 bits (CF, r/m32) right once

D3 /3         RCR r/m32,CL         Rotate 33 bits (CF, r/m32) right CL times

C1 /3 ib         RCR r/m32,imm8         Rotate 33 bits (CF, r/m32) right imm8 times

D0 /0         ROL r/m8,1         Rotate 8 bits r/m8 left once

D2 /0         ROL r/m8,CL         Rotate 8 bits r/m8 left CL times

C0 /0 ib         ROL r/m8,imm8         Rotate 8 bits r/m8 left imm8 times

D1 /0         ROL r/m16,1         Rotate 16 bits r/m16 left once

D3 /0         ROL r/m16,CL         Rotate 16 bits r/m16 left CL times

C1 /0 ib         ROL r/m16,imm8         Rotate 16 bits r/m16 left imm8 times

D1 /0         ROL r/m32,1         Rotate 32 bits r/m32 left once

D3 /0         ROL r/m32,CL         Rotate 32 bits r/m32 left CL times

C1 /0 ib         ROL r/m32,imm8         Rotate 32 bits r/m32 left imm8 times

D0 /1         ROR r/m8,1         Rotate 8 bits r/m8 right once

D2 /1         ROR r/m8,CL         Rotate 8 bits r/m8 right CL times

C0 /1 ib         ROR r/m8,imm8         Rotate 8 bits r/m16 right imm8 times

D1 /1         ROR r/m16,1         Rotate 16 bits r/m16 right once

D3 /1         ROR r/m16,CL         Rotate 16 bits r/m16 right CL times

C1 /1 ib         ROR r/m16,imm8         Rotate 16 bits r/m16 right imm8 times

D1 /1         ROR r/m32,1         Rotate 32 bits r/m32 right once

D3 /1         ROR r/m32,CL         Rotate 32 bits r/m32 right CL times

C1 /1 ib         ROR r/m32,imm8         Rotate 32 bits r/m32 right imm8 times


Description

Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the second operand (count operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in the CL register. The processor restricts the count to a number between 0 and 31 by masking all the bits in the count operand except the 5 least-significant bits.


The rotate left (ROL) and rotate through carry left (RCL) instructions shift all the bits toward more-significant bit positions, except for the most-significant bit, which is rotated to the least-significant bit location (see Figure 6-10 in the Intel Architecture Software Developer's Manual, Vo l u me 1 ). The rotate right (ROR) and rotate through carry right (RCR) instructions shift all the bits toward less significant bit positions, except for the least-significant bit, which is rotated to the most-significant bit location (see Figure 6-10 in the Intel Architecture Software Developer's Manual, Volume 1).


The RCL and RCR instructions include the CF flag in the rotation. The RCL instruction shifts the CF flag into the least-significant bit and shifts the most-significant bit into the CF flag (see Figure 6-10 in the Intel Architecture Software Developer's Manual, Volume 1). The RCR instruction shifts the CF flag into the most-significant bit and shifts the least-significant bit into the CF flag (see Figure 6-10 in the Intel Architecture Software Developer's Manual, Volume 1). For the ROL and ROR instructions, the original value of the CF flag is not a part of the result, but the CF flag receives a copy of the bit that was shifted from one end to the other.


The OF flag is defined only for the 1-bit rotates; it is undefined in all other cases (except that a zero-bit rotate does nothing, that is affects no flags). For left rotates, the OF flag is set to the exclusive OR of the CF bit (after the rotate) and the most-significant bit of the result. For right rotates, the OF flag is set to the exclusive OR of the two most-significant bits of the result.


Operands        Bytes                Clocks

reg, 1               2                  1   PU

mem, 1            2+d(0,2)         3   PU

reg, cl              2                    7-24 NP

mem, cl           2+d(0,2)         9-26 NP

reg, imm             3                  8-25 NP

mem, imm          3+d(0,2)         10-27 NP


Flags

The CF flag contains the value of the bit shifted into it. The OF flag is affected only for single-bit rotates (see "Description" above); it is undefined for multi-bit rotates. The SF, ZF, AF, and PF flags are not affected.

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